The invention concerns the connection of a host computer with a plurality of peripheral devices, and more particularly is directed to connection of the plurality of peripheral devices to the host computer through a port in the host computer.
The connection of peripheral devices to a host computer presents a significant engineering challenge that is compounded as the demand for peripheral device connection grows, while the physical resources necessary to support plural connection to a host computer shrink. Typically, the connection between a host computer and a peripheral device is through a single entity referred to as a port. When used herein, the word "port" implies both the electro-mechanical interface (connector) and associated electronics (logic) that support the transport of information and data between a host computer and a peripheral device.
It is known to connect a plurality of peripheral devices through a single host computer port. See, for example, the communications subsystem described in U.S. Pat. No. 4,845,609, commonly assigned with this patent application and incorporated herein by reference. The communications subsystem is illustrated in FIG. 1.
In FIG. 1, a host computer 10 is connected to a plurality of peripheral devices including peripheral devices 12 and 14 by way of cluster controllers 16 and 17, respectively. The host computer 10 is connected to the cluster controllers 16, 17 by way of a token-passing local area network (LAN) 18 that connects to the host computer 10 through a single LAN port 20. Each of the cluster controllers 16, 17 includes a plurality of serial ports, such as the serial ports 21 on the cluster controller 16.
More specifically, as FIG. 1 illustrates, the host computer 10 includes a plurality of drivers 24, each of which comprises operating system logic for controlling peripheral devices. In this regard, each of the drivers 24 is provided as an operating system routine in the host computer 10 that embodies logic necessary to operate a specific peripheral device. The device drivers 24 are coupled by a driver interface 26 with a host adapter 27 with logic including a host interface handler 28, terminal control tasks 29, and a network manager 30. The host adapter 27 also includes a dual port random access memory (DPRAM) structure 31 for buffering control and status information and data between the device drivers 24 and the peripheral devices 12. The components of the host adapter 27 are coupled by a bus 32 that reflects the specific architecture and functionality of the underlying processor platform. In this regard, the operations of the host interface components 28-31, are taxed by the overhead necessary to conduct operations on the bus 32.
Thus, while the communications subsystem operates with extraordinary effect to couple a plurality of peripheral devices to the host computer 10 through the single LAN port 20, it does require adaptation to the bus architecture of the particular host computer platform on which it is installed.
Further, as is known, the number of card slots for the host computer bus is limited. When all of the modules necessary to host computer operation occupy card slots, the slots remaining are in very short supply. Thus, if the modularized host adapter can be moved outside of the host computer, a scarce data bus slot would be freed.
Last, the prior art communication subsystem is complex and relatively expensive. When used to fan out a single host computer port to many (over 32) peripheral device ports, the subsystem is cost effective. However, for fewer ports, (4-32), the subsystem may not be cost effective.
Accordingly, it should be evident that there is a need to reduce the data bus dependency of a communications subsystem that couples a host computer to a plurality of peripheral devices through a single host computer port, while making the subsystem cost effective for a limited number of ports.